Gaseous discharge display/memory panels of the type to which the present invention pertains are disclosed in Baker et al. U.S. Pat. No. 3,499,167 and in the discussion which follows, the reference to a gaseous discharge display panel is to be had in connection with this type panel. However, another type of panel to which the invention is applicable is disclosed in Bitzer et al. U.S. Pat. No. 3,559,190. Panels are disclosed in these patents have an electrical memory constituted by the storage of charges produced on discharge on one or more dielectric surfaces in contact with the gas. Typically, the electrodes are non-conductively coupled to the gas and in the case of the Baker et al. patent the dielectric is a thin glass coating on each conductor array. The conductors are arrayed in columns and rows to form a cross conductor matrix between which an ionizable gaseous medium, typically a mixture of two gases at a selected pressure is confined in a thin gas chamber spaced therebetween. A preferred gas is a neon-argon gas mixtue as disclosed in Nolan application Ser. No. 764,577 filed Oct. 2, 1968. The dielectric layer permits the passage of any conductive current from the matrix conductor members to the gaseous medium and also serve as collecting surfaces for charges in the ionizable gaseous medium during alternate half-cycles of the periodic operating potentials applied thereto such potentials normally be designated as the sustainer potential.
The discharge condition of the gas between selected row-column conductor pairs is controlled by the application of discharge manipulating pulse potentials which are algebraically added to the sustainer potentials at selected times to initiate sequences of discharges sustainable by the sustainer potential and terminate the sequence of discharges by removal or termination of wall charging at the matrix cross points (see Johnson et al. U.S. Pat. No. 3,618,071).
In such panels there is a critical panel write voltage distribution and, in the same sense there is a critical erase voltage distribution. In accordance with the present invention, the write/erase pedestal voltages are adjusted so as to obtain the maximum operating range for a given display/memory panel. It is possible therefore to set the applied write voltage so that the critical half select voltages will be less than the minimum select voltage for the first firing of any site in the panel (as derived from the critical panel write voltage distribution) and the same applies with respect to the critical panel erase voltage distribution. By following teachings of this invention, the half select problem is minimized and a maximum write/erase window is obtained in addition to an overlap of the two for the operating range.